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ISL43231
Data Sheet September 2003 FN6054
Low-Voltage, Single and Dual Supply, Triple SPDT Analog Switch
The Intersil ISL43231 device is a precision, bidirectional, analog switches configured as a a triple single pole/double throw (SPDT) switch, designed to operate from a single +2V to +12V supply or from a 2V to 6V supply. The device has an inhibit and inhibit bar pin to simultaneously open all signal paths. The device also has a latch bar pin to lock in the last switch address. ON resistance of 39 with a 5V supply and 125 with a +3.3V supply. Each switch can handle rail to rail analog signals. The off-leakage current is only 0.1nA at +25oC or 2.5nA at +85oC. All digital inputs have 0.8V to 2.4V logic thresholds, ensuring TTL/CMOS logic compatibility when using a single +3.3V or +5V supply or dual 5V supplies. The ISL43231 is a committed triple SPDT, which is perfect for use in 2-to-1 multiplexer applications. Table 1 summarizes the performance of this part.
TABLE 1. FEATURES AT A GLANCE CONFIGURATION 5V RON 5V tON/tOFF 12V RON 12V tON/tOFF 5V RON 5V tON/tOFF 3.3V RON 3.3V tON/tOFF Package TRIPLE SPDT 39 32ns/18ns 32 23ns/15ns 65 38ns/19ns 125 70ns/32ns 20 Ld 4x4 QFN
Features
* Fully Specified at 3.3V, 5V, 5V, and 12V Supplies for 10% Tolerances * ON Resistance (RON) Max, VS = 4.5V . . . . . . . . . . . 50 * ON Resistance (RON) Max, VS = +3V . . . . . . . . . . . 155 * RON Matching Between Channels, VS = 5V . . . . . . . . . <2 * Low Charge Injection, VS = 5V . . . . . . . . . . . . . 1pC (Max) * Single Supply Operation. . . . . . . . . . . . . . . . . . . +2V to +12V * Dual Supply Operation . . . . . . . . . . . . . . . . . . . . . 2V to 6V * Fast Switching Action (VS = +5V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19ns * Guaranteed Max Off-leakage . . . . . . . . . . . . . . . . . . . 2.5nA * Guaranteed Break-Before-Make * TTL, CMOS Compatible
Applications
* Battery Powered, Handheld, and Portable Equipment * Communications Systems - Radios - Telecom Infrastructure - ADSL, VDSL Modems * Test Equipment - Medical Ultrasound - Magnetic Resonance Image - CT and PET Scanners (MRI) - ATE - Electrocardiograph * Audio and Video Signal Routing * Various Circuits - +3V/+5V DACs and ADCs - Sample and Hold Circuits - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing - Integrator Reset Circuits
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Application Note AN557 "Recommended Test Procedures for Analog Switches" * Application Note AN520 "CMOS Analog Multiplexers and Switches; Specifications and Application Considerations." * Application Note AN1034 "Analog Switch and Multiplexer Applications"
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved
ISL43231 Pinout
ISL43231 (QFN) TOP VIEW
COMB 16 15 COMC 14 NOC 13 NCC 12 ADDC 11 ADDB 6 -V 7 GND 8 N.C. 9 LE 10 ADDA NOB NCB N.C. 18
20 NOA COMA NCA EN EN 1 2 3 4 5
19
17
Truth Table
ISL43231 LE 0 X X 1 1 1 1 1 1 EN 1 0 X 1 1 1 1 1 1 EN 0 X 1 0 0 0 0 0 0 ADDC ADDB ADDA X X X X X X X 0 1 X X X X X 0 1 X X X X X 0 1 X X X X SWITCH ON Last Switches Selected NONE NONE NCA NOA NCB NOB NCC NOC
+V
Pin Descriptions
PIN V+ VGND EN EN LE COM NO NC ADD N.C. FUNCTION Positive Power Supply Input Negative Power Supply Input. Connect to GND for Single Supply Configurations. Ground Connection Digital Control Input. Connect to GND for Normal Operation. Connect to V+ to turn all switches off. Digital Control Input. Connect to V+ for Normal Operation. Connect to GND to turn all switches off. Digital Control Input. Connect to +V for Normal Operation. Connect to GND to latch the last switch state. Analog Switch Common Pin Analog Switch Normally Open Pin Analog Switch Normally Closed Pin Address Input Pin No Internal Connection
NOTE: Logic "0" 0.8V. Logic "1" 2.4V, with V+ between 2.7V and 10V. X = Don't Care.
Ordering Information
PART NO. (BRAND) ISL43231IR (741I) TEMP. RANGE (oC) -40 to 85 PACKAGE 20 Ld QFN PKG. DWG. # L20.4x4
2
ISL43231
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to 0.3V Input Voltages LE, EN, EN, NO, NC, ADD (Note 1) . . . . . . . -0.3 to ((V+) + 0.3V) Output Voltages COM (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . 30mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 100mA ESD Rating HBM ( Per Mil-STD-883, Method 3015.7) . . . . . . . . . . . . . >2.5kV
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) 20 Ld 4x4 QFN Package . . . . . . . . . . . . . . . . . . . . . 45 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (Lead Tips Only)
Operating Conditions
Temperature Range ISL43231IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Signals on NC, NO, COM, ADD, EN, EN, or LE exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. JA is measured with the component mounted on a high effective thermal conductivity test board with direct die attach features. See Tech Brief TB379 for details.
Electrical Specifications 5V Supply
Test Conditions: VSUPPLY = 4.5V to 5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) (NOTE 4) MIN TYP (NOTE 4) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full VS = 4.5V, ICOM = 2mA, VNO or VNC = 3V (See Figure 6) VS = 4.5V, ICOM = 2mA, VNO or VNC = 3V (Note 5) 25 Full 25 Full VS = 4.5V, ICOM = 2mA, VNO or VNC = 3V, 0V (Note 6) VS = 5.5V, VCOM = 4.5V, VNO or VNC = +4.5V (Note 7) VS = 5.5V, VCOM = 4.5V, VNO or VNC = +4.5V (Note 7) VS = 5.5V, VCOM = VNO or VNC = 4.5V (Note 7) 25 Full 25 Full 25 Full 25 Full
V-0.1 -2.5 -0.1 -2.5 -0.1 -2.5
44 1.3 7.5 0.002 0.002 0.002 -
V+ 50 80 4 6 9 12 0.1 2.5 0.1 2.5 0.1 2.5
V nA nA nA nA nA nA
RON Matching Between Channels, RON RON Flatness, RFLAT(ON)
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM OFF Leakage Current, ICOM(OFF) COM ON Leakage Current, ICOM(ON)
DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH, VADDH Input Voltage Low, VINL, VADDL Input Current, IADDH, IADDL, IENH, IENL Input Current, IENH, ILEH Input Current, IENL, ILEL VS = 5.5V, VINH, VADD = 0V or V+ VS = 5.5V, VINH, VADD = 0V or V+ VS = 5.5V, VINH, VADD = 0V or V+ Full Full Full Full Full 2.4 -0.5 -1.5 -4 0.8 0.5 1.5 4 V V A A A
3
ISL43231
Electrical Specifications 5V Supply
Test Conditions: VSUPPLY = 4.5V to 5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3), Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (oC) (NOTE 4) MIN TYP (NOTE 4) MAX UNITS
PARAMETER DYNAMIC CHARACTERISTICS Enable Turn-ON Time, tON
VS = 4.5V, VNO or VNC = 3V, RL =300, CL = 35pF, VIN = 0 to 3 (See Figure 1) VS = 4.5V, VNO or VNC = 3V, RL =300, CL = 35pF, VIN = 0 to 3 (See Figure 1) VS = 4.5V, VNO or VNC = 3V, RL =300, CL = 35pF, VIN = 0 to 3 (See Figure 1) VS = 5.5V, VNO or VNC = 3V, RL = 300, CL = 35pF, VIN = 0 to 3V (See Figure 3) (See Figure 4)
25 Full 25 Full 25 Full Full 25 Full
2 25 35 0 0 15 25 -
35 22 43 7 0.3 3 9 14 92 <-110 -105
50 60 35 40 60 70 1 1.5
ns ns ns ns ns ns ns ns ns ns ns ns ns pC pF pF pF dB dB dB
Enable Turn-OFF Time, tOFF
Address Transition Time, tTRANS
Break-Before-Make Time, tBBM Latch Setup Time, tS
Latch Hold Time, tH
(See Figure 4)
25 Full
Latch Pulse Width, tWPW
(See Figure 4)
25 Full
Charge Injection, Q NO/NC OFF Capacitance, COFF COM OFF Capacitance, COFF COM ON Capacitance, CCOM(ON) OFF Isolation Crosstalk (Note 8) All Hostile Crosstalk (Note 8)
CL = 1.0nF, VG = 0V, RG = 0 (See Figure 2) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 8) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 8) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 8) RL = 50, CL = 15pF, f = 100kHz, VNOx or VNCx = 1VRMS (See Figures 5, 7 and 20)
25 25 25 25 25 25 25
POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ Negative Supply Current, INOTES: 3. VIN = Input logic voltage to configure the device in a given state. 4. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 5. RON = RON (MAX) - RON (MIN). 6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25oC. 8. Between any two switches. VS = 5.5V, VINH, VADD = 0V or V+, Switch On or Off Full Full Full 2 -7 -1 6 7 1 V A A
Electrical Specifications +12V Supply
Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 3), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) (NOTE 4) MIN TYP (NOTE 4) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG
Full
0
-
V+
V
4
ISL43231
Electrical Specifications +12V Supply
Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 3), Unless Otherwise Specified (Continued) TEST CONDITIONS V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 9V (See Figure 6) V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 9V (Note 5) TEMP (oC) 25 Full 25 Full V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 3V, 6V, 9V (Note 6) V+ = 13.2V, VCOM = 1V, 12V, VNO or VNC = 12V, 1V (Note 7) V+ = 13.2V, VCOM = 12V, 1V, VNO or VNC = 1V, 12V (Note 7) V+ = 13.2V, VCOM = 1V, 12V, VNO or VNC = 1V, 12V, or floating (Note 7) 25 Full 25 Full 25 Full 25 Full (NOTE 4) MIN -0.1 -2.5 -0.1 -2.5 -0.1 -2.5 TYP 37 1.2 5 0.002 0.002 0.002 (NOTE 4) MAX UNITS 45 55 2 2 7 7 0.1 2.5 0.1 2.5 0.1 2.5 nA nA nA nA nA nA
PARAMETER ON Resistance, RON
RON Matching Between Channels, RON RON Flatness, RFLAT(ON)
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM OFF Leakage Current, ICOM(OFF) COM ON Leakage Current, ICOM(ON)
DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH, VADDH Input Voltage Low, VINL, VADDL Input Current, IADDH, IADDL, IENH, IENL Input Current, IENH, ILEH Input Current, IENL, ILEL DYNAMIC CHARACTERISTICS Enable Turn-ON Time, tON V+ = 10.8V, VNO or VNC = 10V, RL =300, CL = 35pF, VIN = 0 to 4 (See Figure 1) V+ = 10.8V, VNO or VNC = 10V, RL =300, CL = 35pF, VIN = 0 to 4 (See Figure 1) V+ = 10.8V, VNO or VNC = 10V, RL =300, CL = 35pF, VIN = 0 to 4 (See Figure 1) V+ = 13.2V, RL = 300, CL = 35pF, VNO or VNC = 10V, VIN = 0 to 4 (See Figure 3) (See Figure 4) 25 Full 25 Full 25 Full Full 25 Full Latch Hold Time, tH (See Figure 4) 25 Full Latch Pulse Width, tWPW (See Figure 4) 25 Full Charge Injection, Q OFF Isolation Crosstalk, Note 8 All Hostile Crosstalk, Note 8 NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 8) CL = 1.0nF, VG = 0V, RG = 0 (See Figure 2) RL = 50, CL = 15pF, f = 100kHz, VNOx or VNCx= 1VRMS (See Figures 5, 7 and 20) 25 25 25 25 25 2 25 35 0 0 15 25 27 5 2.7 92 <-110 -105 3 15 24 40 45 30 35 50 55 5 1.5 ns ns ns ns ns ns ns ns ns ns ns ns ns pC dB dB dB pF V+ = 13.2V, VINH, VADD = 0V or V+ V+ = 13.2V, VINH, VADD = 0V or V+ V+ = 13.2V, VINH, VADD = 0V or V+ Full Full Full Full Full 3.7 -0.5 -1.5 -4 3.3 2.7 0.8 0.5 1.5 4 V V A A A
Enable Turn-OFF Time, tOFF
Address Transition Time, tTRANS
Break-Before-Make Time Delay, tD Latch Setup Time, tS
5
ISL43231
Electrical Specifications +12V Supply
Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 3), Unless Otherwise Specified (Continued) TEST CONDITIONS f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 8) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 8) TEMP (oC) 25 25 (NOTE 4) MIN TYP 9 14 (NOTE 4) MAX UNITS pF pF
PARAMETER COM OFF Capacitance, CCOM(OFF) COM ON Capacitance, CCOM(ON)
POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ Positive Supply Current, IV+ = 13.2V, VINH, VADD = 0V or V+, all channels on or off Full Full Full 2 -7 -1 12 7 1 V A A
Electrical Specifications 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) MIN (NOTE 4) TYP MAX (NOTE 4) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V (See Figure 6) V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3V (Note 5) 25 Full 25 Full V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 1V, 2V, 3V (Note 6) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V (Note 7) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V (Note 7) V+ = 5.5V, VCOM = VNO or VNC = 4.5V (Note 7) 25 Full 25 Full 25 Full 25 Full
0 -0.1 -2.5 -0.1 -2.5 -0.1 -2.5
81 2.2 11.5 0.002 0.002 0.002 -
V+ 90 120 4 6 17 24 0.1 2.5 0.1 2.5 0.1 2.5
V nA nA nA nA nA nA
RON Matching Between Channels, RON RON Flatness, RFLAT(ON)
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM OFF Leakage Current, ICOM(OFF) COM ON Leakage Current, ICOM(ON)
DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH, VADDH Input Voltage Low, VINL, VADDL Input Current, IADDH, IADDL, IENH, IENL Input Current, IENH, ILEH Input Current, IENL, ILEL DYNAMIC CHARACTERISTICS Enable Turn-ON Time, tON V+ = 4.5V, VNO or VNC = 3V, RL = 300, CL = 35pF, VIN = 0 to 3V (See Figure 1) V+ = 4.5V, VNO or VNC = 3V, RL = 300, CL = 35pF, VIN = 0 to 3V (See Figure 1) V+ = 4.5V, VNO or VNC = 3V, RL = 300, CL = 35pF, VIN = 0 to 3V (See Figure 1) 25 Full 25 Full 25 Full 43 20 51 60 70 35 40 70 85 ns ns ns ns ns ns V+ = 5.5V, VINH, VADD = 0V or V+ V+ = 5.5V, VINH, VADD = 0V or V+ V+ = 5.5V, VINH, VADD = 0V or V+ Full Full Full Full Full 2.4 -0.5 -1.5 -4 0.8 0.5 1.5 4 V V A A A
Enable Turn-OFF Time, tOFF
Address Transition Time, tTRANS
6
ISL43231
Electrical Specifications 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3), Unless Otherwise Specified (Continued) TEST CONDITIONS V+ = 5.5V, VNO or VNC = 3V, RL = 300, CL = 35pF, VIN = 0 to 3V (See Figure 3) (See Figure 4) TEMP (oC) Full 25 Full Latch Hold Time, tH (See Figure 4) 25 Full Latch Pulse Width, tWPW (See Figure 4) 25 Full Charge Injection, Q OFF Isolation Crosstalk, Note 8 All Hostile Crosstalk, Note 8 POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ Positive Supply Current, IV+ = 5.5V, V- = 0V, VINH, VADD = 0V or V+, Switch On or Off Full Full Full 2 -7 -1 12 7 1 V A A CL = 1.0nF, VG = 0V, RG = 0 (See Figure 2) RL = 50, CL = 15pF, f = 100kHz, VNOx or VNCx= 1VRMS (See Figures 5, 7 and 20) 25 25 25 25 MIN (NOTE 4) 2 25 35 0 0 15 25 TYP 9 0.6 92 <-110 -105 MAX (NOTE 4) UNITS 1.5 1.5 ns ns ns ns ns ns ns pC dB dB dB
PARAMETER Break-Before-Make Time, tBBM Latch Setup Time, tS
Electrical Specifications 3.3V Supply
Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) MIN (NOTE 4) TYP MAX (NOTE 4) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 3.0V, ICOM = 1.0mA, VNO or VNC = 1.5V (See Figure 6) V+ = 3.0V, ICOM = 1.0mA, VNO or VNC = 1.5V (Note 5) 25 Full 25 Full V+ = 3.0V, ICOM = 1.0mA, VNO or VNC = 0.5V, 1V, 2V (Note 6) V+ = 3.6V, VCOM = 0V, 4.5V, VNO or VNC = 3V, 1V (Note 7) V+ = 3.6V, VCOM = 0V, 4.5V, VNO or VNC = 3V, 1V (Note 7) V+ = 3.6V, VCOM = VNO or VNC = 3V (Note 7) 25 Full 25 Full 25 Full 25 Full
0 -0.1 -2.5 -0.1 -2.5 -0.1 -2.5
135 3.4 34 0.002 0.002 0.002 -
V+ 155 200 8 10 40 50 0.1 2.5 0.1 2.5 0.1 2.5
V nA nA nA nA nA nA
RON Matching Between Channels, RON RON Flatness, RFLAT(ON)
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM OFF Leakage Current, ICOM(OFF) COM ON Leakage Current, ICOM(ON)
DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH, VADDH Input Voltage Low, VINL, VADDL Input Current, IADDH, IADDL, IENH, IENL V+ = 3.6V, VINH, VADD = 0V or V+ Full Full Full 2.4 -0.5 0.8 0.5 V V A
7
ISL43231
Electrical Specifications 3.3V Supply
Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 3), Unless Otherwise Specified (Continued) TEST CONDITIONS V+ = 3.6V, VINH, VADD = 0V or V+ V+ = 3.6V, VINH, VADD = 0V or V+ TEMP (oC) Full Full MIN (NOTE 4) -1.5 -4 TYP MAX (NOTE 4) UNITS 1.5 4 A A
PARAMETER Input Current, IENH, ILEH Input Current, IENL, ILEL DYNAMIC CHARACTERISTICS Enable Turn-ON Time, tON
V+ = 3.0V, VNO or VNC = 1.5V, RL = 300, CL = 35pF, VIN = 0 to 3V (See Figure 1) V+ = 3.0V, VNO or VNC = 1.5V, RL = 300, CL = 35pF, VIN = 0 to 3V (See Figure 1) V+ = 3.0V, VNO or VNC = 1.5V, RL = 300, CL = 35pF, VIN = 0 to 3V (See Figure 1) V+ = 3.6V, VNO or VNC = 1.5V, RL = 300, CL = 35pF, VIN = 0 to 3V (See Figure 3) (See Figure 4)
25 Full 25 Full 25 Full Full 25 Full
3 50 60 0 0 30 40 -
82 37 96 13 0.3 92 <-110 -105
100 120 50 60 120 145 1 1.5
ns ns ns ns ns ns ns ns ns ns ns ns ns pC dB dB dB
Enable Turn-OFF Time, tOFF
Address Transition Time, tTRANS
Break-Before-Make Time, tBBM Latch Setup Time, tS
Latch Hold Time, tH
(See Figure 4)
25 Full
Latch Pulse Width, tWPW
(See Figure 4)
25 Full
Charge Injection, Q OFF Isolation Crosstalk, Note 8 All Hostile Crosstalk, Note 8
CL = 1.0nF, VG = 0V, RG = 0 (See Figure 2) RL = 50, CL = 15pF, f = 100kHz, VNOx or VNCx= 1VRMS (See Figures 5, 7 and 20)
25 25 25 25
POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ Positive Supply Current, IV+ = 3.6V, V- = 0V, VINH, VADD = 0V or V+, Switch On or Off Full Full Full 2 -7 -1 12 7 1 V A A
8
ISL43231 Test Circuits and Waveforms
3V LOGIC INPUT 50% 0V tON EN, LE V+ NCX NOX VNCX SWITCH OUTPUT 0V tOFF 90% VOUT 90% LOGIC INPUT EN GND COMX ADDX VOUT tr < 20ns tf < 20ns V+ C C VC
RL 300
CL 35pF
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L ( ON ) FIGURE 1B. ENABLE tON / tOFF TEST CIRCUIT
FIGURE 1A. ENABLE tON / tOFF MEASUREMENT POINTS
3V LOGIC INPUT 0V tTRANS 50%
tr < 20ns tf < 20ns
V+ C
C
V-
C
V+ VC 90%
NCX EN, LE NOX COMX EN RL 300 VOUT
VNCX SWITCH OUTPUT
VOUT
ADDX 0V 10% VNOX tTRANS LOGIC INPUT
GND
CL 35pF
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L ( ON ) FIGURE 1D. ADDRESS tTRANS TEST CIRCUIT
FIGURE 1C. ADDRESS tTRANS MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
V+
C
V-
C
3V LOGIC INPUT OFF ON 0V OFF RG 0 SWITCH OUTPUT VOUT Q = VOUT x CL VOUT VG ADDX GND EN LOGIC INPUT CL 1nF EN, LE NOX or NCX COMX VOUT
FIGURE 2A. Q MEASUREMENT POINTS
Repeat test for other switches. FIGURE 2B. Q TEST CIRCUIT FIGURE 2. CHARGE INJECTION
9
ISL43231 Test Circuits and Waveforms
3V LOGIC INPUT 0V
(Continued)
tr < 20ns tf < 20ns C EN, LE V+ NCX, NOX ADDX VOUT COMX RL 300 CL 35pF V+ C VC
SWITCH OUTPUT VOUT 0V tBBM
80%
LOGIC INPUT
GND
EN
Repeat test for other switches. CL includes fixture and stray capacitance. FIGURE 3A. tBBM MEASUREMENT POINTS FIGURE 3B. tBBM TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
tMPW LOGIC INPUT LE 3V 50% 0V tH tS 50% 50%
tr < 20ns tf < 20ns
V+
C
V-
C
C
EN tH ADDX LOGIC INPUT LE LOGIC INPUT
NCX NOX COMX VOUT
V+
LOGIC INPUT ADDX
3V 50% 0V tON, tOFF 50%
GND EN
RL 300
CL 35pF
VNCX SWITCH OUTPUT 0V
VOUT
90%
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for other switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------------R L + R ( ON ) FIGURE 4B. LATCH tS, tH, tMPW TEST CIRCUIT
FIGURE 4A. LATCH tS, tH, tMPW MEASUREMENT POINTS
FIGURE 4. LATCH SETUP AND HOLD TIMES
V+
C
V-
C
V+
C
V-
C
SIGNAL GENERATOR
EN, LE
NO or NC
RON = V1/1mA
EN, LE NO or NC
VNX 0V or V+ ADDX 0V or V+
COM
1mA
V1
0V or V+ ADDX
ANALYZER RL
GND
EN
COM
GND
EN
FIGURE 5. OFF ISOLATION TEST CIRCUIT
FIGURE 6. RON TEST CIRCUIT
10
ISL43231 Test Circuits and Waveforms
V+ C
(Continued)
V-
C
V+
C
V-
C
SIGNAL GENERATOR
EN, LE NOA or NCA COMA
50
EN, LE NO or NC 0V or V+
0V or V+
ADDX
IMPEDANCE ANALYZER NOB or NCB N.C. COM
ADDX
ANALYZER RL
COMB
GND
EN
GND
EN
FIGURE 7. CROSSTALK TEST CIRCUIT
FIGURE 8. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL43231 analog switch offers a precise switching capability from a bipolar 2V to 6V or a single 2V to 12V supply with low on-resistance (39) and high speed operation (tON = 38ns, tOFF = 19ns) with dual 5V supplies. It has an inhibit and inhibit bar pin to simultaneously open all signal paths. It also has a latch bar pin to lock in the last switch address. The device is especially well suited for applications using 5V supplies. With 5V supplies the performance (RON, Leakage, Charge Injection, etc.) is best in class. High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection.
diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 9). These additional diodes limit the analog signal from 1V below V+ to 1V above V-. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages.
OPTIONAL PROTECTION RESISTOR FOR LOGIC INPUTS V+
OPTIONAL PROTECTION DIODE
1k
LOGIC VNO or NC VCOM
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to V- (see Figure 9). To prevent forward biasing these diodes, V+ and V- must be applied before any input signals, and input signal voltages must remain between V+ and V-. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (see Figure 9). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not applicable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal 11
VOPTIONAL PROTECTION DIODE
FIGURE 9. INPUT OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL43231 construction is typical of most CMOS analog switches, in that they have three supply pins: V+, V-, and GND. V+ and V- drive the internal CMOS switches and set their analog voltage limits, so there are no connections between the analog signal path and GND. Unlike switches with a 13V maximum supply voltage, the ISL43231 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies (6V or 12V single supply), as well as room for overshoot and noise spikes. This switch device performs equally well when operated with bipolar or single voltage supplies.The minimum recommended supply voltage is 2V or 2V. It is important to
ISL43231
note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. V+ and GND power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switched V+ and V- signals to drive the analog switch gate terminals. resistance to this feed through, while Crosstalk indicates the amount of feed through from one switch to another. Figure 20 details the high Off Isolation and Crosstalk rejection provided by this family. At 10MHz, Off Isolation is about 55dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance.
Logic-Level Thresholds
V+ and GND power the internal logic stages, so V- has no affect on logic thresholds. This switch family is TTL compatible (0.8V and 2.4V) over a V+ supply range of 2.7V to 10V. At 12V the VIH level is about 3.3V. This is still below the CMOS guaranteed high output minimum level of 4V, but noise margin is reduced. For best results with a 12V supply, use a logic family that provides a VOH greater than 4V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation.
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and V-. One of these diodes conducts if any analog signal exceeds V+ or V-. Virtually all the analog leakage current comes from the ESD diodes to V+ or V-. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or V- and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and V- pins constitutes the analog-signalpath leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and GND.
High-Frequency Performance
In 50 systems, signal response is reasonably flat even past 100MHz (see Figures 18 and 19). Figures 18 and 19 also illustrates that the frequency response is very consistent over varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch's input to its output. Off Isolation is the
Typical Performance Curves TA = 25oC, Unless Otherwise Specified
70 60 50 40 30 RON () 20 400 V- = 0V 300 200 100 0 V- = -5V VCOM = (V+) - 1V ICOM = 1mA 85oC 25oC -40oC 120 110 100 90 80 70 60 50 90 80 70 60 50 40 30 60 50 40 30 2 3 4 5 6 7 V+ (V) 8 9 10 11 12 20 -5 -4 -3 -2 -1 1 0 VCOM (V) 2 3 4 5 -40oC ICOM = 1mA 85oC 25oC -40oC VS = 3V VS = 2V
RON ()
85oC 25oC -40oC
85oC -40oC
25oC
25oC
85oC
VS = 5V
FIGURE 10. ON RESISTANCE vs SUPPLY VOLTAGE
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE
12
ISL43231 Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued)
225 200 175 150 125 100 75 160 140 120 100 80 60 100 90 80 70 60 50 40 0 85oC 25oC -40oC V+ = 2.7V V- = 0V RON () ICOM = 1mA 60 55 50 45 85oC 40 35 30 85oC 25oC -40oC 1 3 2 VCOM (V) 4 5 V+ = 5V V- = 0V 25 -40oC 20 0 2 4 6 VCOM (V) 8 10 12 25oC V+ = 12V V- = 0V ICOM = 1mA
RON ()
85oC 25oC -40oC V+ = 3.3V V- = 0V
FIGURE 12. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 13. ON RESISTANCE vs SWITCH VOLTAGE
500 400 300 200 100 tON (ns) 0 250 200 150 100 50 0 2 3 4 5 6 7 V+ (V) 8 9 10 11 12 -40oC -40oC V- = 0V 85oC 25oC V- = -5V -40oC 25oC 25oC 85oC tOFF (ns) VCOM = (V+) - 1V
200 -40oC 150 100 50 0 100 80 60 40 20 0 2 -40oC 3 4 5 6 7 V+ (V) 8 9 10 11 12 -40oC V- = 0V 85oC 25oC 25oC 25oC 85oC V- = -5V VCOM = (V+) - 1V
FIGURE 14. ENABLE TURN - ON TIME vs SUPPLY VOLTAGE
FIGURE 15. ENABLE TURN - OFF TIME vs SUPPLY VOLTAGE
300
VCOM = (V+) - 1V V- = 0V
250 VCOM = (V+) - 1V 200
250
tRANS (ns)
tRANS (ns)
200
150
150
100
25oC 85oC
100
25oC 85oC 50 -40oC 0 2 3 4 5 6 7 8 9 10 11 12 13 2 3 4
50 -40oC 0 V+ (V)
5
6
V (V)
FIGURE 16. ADDRESS TRANS TIME vs SINGLE SUPPLY VOLTAGE
FIGURE 17. ADDRESS TRANS TIME vs DUAL SUPPLY VOLTAGE
13
ISL43231 Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued)
NORMALIZED GAIN (dB) VS = 5V 3 GAIN 0 -3 NORMALIZED GAIN (dB) VIN = 0.2VP-P to 5VP-P VS = 3V 3 GAIN 0 -3 VIN = 0.2VP-P to 4VP-P
PHASE (DEGREES)
PHASE
PHASE
45 90 135 180 RL = 50 1 10 100 FREQUENCY (MHz) 600
45 90 135 180 RL = 50 1 10 100 FREQUENCY (MHz) 600
FIGURE 18. FREQUENCY RESPONSE
FIGURE 19. FREQUENCY RESPONSE
-10 V+ = 3V to 12V or -20 VS = 2V to 5V RL = 50 -30 -40 CROSSTALK (dB) -50 -60 ISOLATION -70 CROSSTALK -80 -90 -100 ALL HOSTILE CROSSTALK -110 1k 10k 100k 1M 10M
10 20 30 OFF ISOLATION (dB) 40 50 60 70 80 90
3
2 V+ = 3.3V V- = 0V V+ = 12V V- = 0V V+ = 5V V- = 0V VS = 5V -2
1
0 Q (pC)
-1
-3 100 110 100M 500M -4 -5 -2.5 0 2.5 VCOM (V) 5 7.5 10 12
FREQUENCY (Hz)
FIGURE 20. CROSSTALK AND OFF ISOLATION
FIGURE 21. CHARGE INJECTION vs SWITCH VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 193 PROCESS: Si Gate CMOS
14
PHASE (DEGREES)
0
0
ISL43231 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L20.4x4
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VGGD-1 ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 5 0.25 0.35 1.95 1.95 0.18 MIN 0.80 NOMINAL 0.90 0.20 REF 0.23 4.00 BSC 3.75 BSC 2.10 4.00 BSC 3.75 BSC 2.10 0.50 BSC 0.60 20 5 5 0.60 12 0.75 0.15 2.25 2.25 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 1 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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